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Bus architecture for 600-MHz 4.5-Mb DDR SRAM

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8 Author(s)
Kawasumi, A. ; Microelectron. Eng. Lab., Toshiba Corp., Yokohama, Japan ; Suzuki, A. ; Hatada, H. ; Kobayashi, T.
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A double data rate (DDR) SRAM bus architecture which can eliminate any speed penalty for doubling the I/O frequency and support single data rate (SDR) compatibility has been proposed. A method to guarantee data coherency for both DDR and SDR has also been described. With this architecture, we developed a 4.5 Mb DDR SRAM. Under the typical 2.5 V condition, a 600 MHz I/O frequency was achieved.

Published in:

VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on

Date of Conference:

11-13 June 1998