By Topic

A low-power SRAM using improved charge transfer sense amplifiers and a dual-Vth CMOS circuit scheme

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
I. Fukushi ; Fujitsu Labs. Ltd., Kawasaki, Japan ; R. Sasagawa ; M. Hamaminato ; T. Izawa
more authors

In this paper we propose an improved version of the charge transfer sense amplifier (CT sense amp) which completely compensates the threshold voltage (Vth) difference of MOSFETs. We also present a dual-Vth CMOS circuit scheme that enables high speed operation and low leakage power consumption at low supply voltage. A low-power, low-voltage 2 k/spl times/16 b SRAM macro was designed and fabricated using a 0.25 /spl mu/m process. It showed stable operation with an access time of 7.0 ns and power consumption of 3.9 mW at 1.0 V (boost 1.5 V), 100 MHz, 85/spl deg/C.

Published in:

VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on

Date of Conference:

11-13 June 1998