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The operation voltage of VLSIs is ever decreasing due to the strong needs for low-power consumption. In order to achieve low-voltage, high-speed operation, the CMOS process tends to be optimized for low-voltage operation using thinner gate oxide and shorter effective channel length. The low-voltage operation is also important in the future VLSIs, where scaled MOSFETs can be operated only in low V/sub DD/ environments with sufficient reliability. Low-voltage SRAM schemes have been proposed, including source voltage driving and dynamic boost of the supply voltage and word line. However, in these schemes the gate voltage of MOSFETs goes up to over 1.4 V even though the V/sub DD/ is 0.8 V, which gives rise to reliability issues in these cases. In this paper, a sub-volt SRAM circuit scheme is presented which speeds up the conventional low-voltage SRAM by more than a factor of two without applying excessive voltage to gate oxide and with maintaining the subthreshold leakage current to a tolerable level.