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Parallel condition-code generation for high-frequency PowerPC microprocessors

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2 Author(s)
Burns, J.L. ; Res. Lab., IBM Corp., Austin, TX, USA ; Nowka, K.J.

Improving the speed and performance of microprocessors requires aggressive leveraging of the interplay of microarchitecture and circuit design. We describe a unique, high-frequency dataflow macro for accelerating conditional-branch resolution by computing condition codes in parallel with computing the corresponding arithmetic results. This macro improves the microarchitecture by reducing conditional-branch latency while achieving high speed through a pulse-node, delayed-reset dynamic circuit implementation. The design has been realized in a 64-bit PowerPC integer processor that operates at 1.0 GHz (0.15 micron CMOS process).

Published in:

VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on

Date of Conference:

11-13 June 1998

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