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A 2.5 V, 2.0 GByte/s packet-based SDRAM with a 1.0 Gbps/pin interface

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13 Author(s)
Kim, C. ; Memory Div., Samsung Electron. Co. Ltd., Kyungi, South Korea ; Kyung, K.-H. ; Jeong, W.-P. ; Kim, J.-S.
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A 2.5 V, 72 Mbit packet protocol based SDRAM (PSDRAM) achieving a peak bandwidth of 2.0 GByte/s has been developed with a 0.23 /spl mu/m twin-well, 4-poly, 2-metal CMOS process. An internal Vcc of 2.0 V and V/sub term/ of 1.8 V with 0.8 V signal swing are used in the array to reduce the sensing power and I/O switching power, respectively. The total maximum chip power consumption of 1.80 W, including the average I/O switching power of 0.25 W, has been achieved when internal 16 banks are interleavingly operated with 20 ns interval commands at 2.0 GByte/s, Vcc=2.7 V, and T=25/spl deg/C.

Published in:

VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on

Date of Conference:

11-13 June 1998

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