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Multi Gbit-scale partially frozen (PF) NAND DRAM with SDRAM compatible interface

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2 Author(s)
Fujino, T. ; ULSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan ; Arimoto, K.

In order to realize Gbit-scale DRAM in a small chip size, the NAND DRAM cell is a good candidate, however, open bit line (BL) arrangement and multiplexed sensing is necessary as used in a conventional NAND DRAM. We propose a novel PF-NAND cell which achieve the folded BL arrangement and non-multiplexed sensing. A new sense amplifier which is preferable for low voltage operated NAND DRAM is also developed. Furthermore, an SDRAM compatible interface is realized by introducing cache SRAM and wide-band I/O array architecture between the PF-NAND DRAM and cache SRAM.

Published in:

VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on

Date of Conference:

11-13 June 1998