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An on-chip timing adjuster with sub-100-ps resolution for a high-speed DRAM interface

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5 Author(s)
Noda, H. ; Semicond. & IC Div., Hitachi Ltd., Tokyo, Japan ; Aoki, M. ; Tanaka, H. ; Nagahima, O.
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A novel fully digital fine-delay generator for a high-speed DRAM interface is proposed. The generator consists of arrayed delay components and generates a group of rail-to-rail delayed signals with sub-100-ps resolution. The input-coupling element (squeezer) in the delay component converges the variations of the resolution. A test device design using 0.35-/spl mu/m technology demonstrates that a resolution of 26 ps can be realized. A timing adjuster using the generator has 2-clock-cycle lock-in time and sub-100-ps error.

Published in:

VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on

Date of Conference:

11-13 June 1998