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A compact ring delay line for high speed synchronous DRAM

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5 Author(s)
Seong-Jin Jang ; Design Dept., LG Semicon Co. Ltd., Seoul, South Korea ; Seong-Ho Han ; Chang-Sun Kim ; Young-Hyun Jun
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We proposed a compact delay line scheme, ring delay line (RDL). It has a ring topology instead of linear one. The ring time-to-digital converter (TDC) works with wide range of operating frequencies with the help of a shift register. Since the silicon area of ring TDC is negligible, RDL consumes about half of the other linear delay line's area. Its locking time is found to be 2 clock cycles and operating current is less than 1 mA.

Published in:

VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on

Date of Conference:

11-13 June 1998

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