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A new technique for standby leakage reduction in high-performance circuits

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3 Author(s)
Ye, Y. ; Microcomputer. Res. Labs., Intel Corp., Hillsboro, OR, USA ; Borkar, S. ; De, V.

A new standby leakage control technique, which exploits the leakage reduction offered by transistor stacks with "more than one 'off' device", demonstrates 2/spl times/ reduction in standby leakage power for a 32-bit static CMOS adder in a low-Vt, sub-1V, 0.1 /spl mu/m technology. Leakage reduction is achieved with minimal overheads in area, power and process technology. The dynamics of leakage reduction due to transistor stacks, and its influence on the overall leakage power of large circuits are elucidated for the first time.

Published in:

VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on

Date of Conference:

11-13 June 1998

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