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This work describes the implementation of a low power IDCT chip targetted to medium and low bitrate applications. Our strategy for reducing the chip power was two-fold: first, we selected an IDCT algorithm that minimizes activity by exploiting the relative occurence of zero-valued DCT coefficients in compressed video. Previous IDCT implementations have relied on conventional fast IDCT algorithms that perform a constant number of operations per block independent of the data distribution. Our approach performs a variable number of operations that depends on the statistical properties of the input data. Second, we minimized the energy through aggressive voltage scaling using deep pipelining and appropriate circuit techniques so that the chip could produce 14 Msamples/sec (640x480, 30 fps, 4:2:0) at 1.3V in a standard 3.3V process (VTP = -0.9V, VTN=0.7V) and meet the requirement for MPEG2 MP@ML.
Date of Conference: 11-13 June 1998