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Through-silicon-via (TSV) technology permits devices to be placed in the third dimension. Currently, there is a strong motivation for the semiconductor industry to move to 3-D integration using the TSV approach due to its many advantages. However, there are some challenges for TSV wafer processes. One of the challenges is TSV wafer thinning process (WTP). In this paper, a dynamic finite element modeling methodology was established and used to study the TSV WTP-induced wafer stress. It was found that wafer surface roughness, TSV wafer thickness, bonding/debonding material, and TSV feature size have impact on TSV wafer stress under the TSV WTP. The impact of wafer thinning-induced stress on mobility change was also discussed in this paper.