Referenced Items are not available for this document.
A new clock-feedthrough compensation scheme for switched-current circuits is proposed. The scheme is especially suited for the design of delay lines for high-frequency operation. The circuit operates by using an improved two-step technique, in which the input is sampled in a parallel combination of a coarse and a fine memory transistor. Since both transistors are of the same type, large switching transients compared to the conventional S2I scheme can be avoided. Using the proposed circuit, the coarse memory has considerably more time to settle. Compared to the simple cell, the circuit solution requires only one extra switch and one additional clock phase
Published in:
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
(Volume:45
,
Issue:
6
)
Date of Publication: Jun 1998
- Page(s):
- 739 - 743
- ISSN :
- 1057-7130
- INSPEC Accession Number:
- 5957730
- Digital Object Identifier :
- 10.1109/82.686693
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Jun 1998
- Sponsored by :
- IEEE Circuits and Systems Society
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