Low power VLSI DS/FH hybrid CDMA spread spectrum IF/baseband transceiver design

A low power digital VLSI baseband transceiver design methodology based on the formulation of empirical power consumption and a system performance model is presented. The method is applied in designing a low-power single chip VLSI solution which implements an architecture for an all-digital binary phase shift keyed (BPSK) direct-sequence (DS) spread spectrum combined with frequency-hopping (FH) technique. The architecture incorporates a low complexity digital Costas loop for carrier recovery and a delay-locked loop for clock recovery. For the pseudo-random noise (PN) sequence acquisition, an energy detection scheme is incorporated. The discussed architecture is intended for use in very high spread spectrum radio band and with various data type processing capability such as image, video, audio, as well as text data. The proposed method formulates the relationships between the circuitry processing power consumed by the transceiver chip architecture and the performance of the transceiver system over the wide range of data rates, processing gains, and signal-to-noise ratios (SNR). The model provides the insights into the system design trade-offs to be made during the low-power transceiver system design process. Individual key digital processing component comprising the system is implemented in 0.6 microns CMOS technology from which the power consumption information is extracted. System performance sensitive functional DSP modules are identified and analyzed including the finite word-length effects on the overall transceiver performance