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A 45 Mb/s high speed performance monitoring chip for digital transmission system

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6 Author(s)

A 45-Mb/s DS-3 performance monitoring chip, the PM45M, has been designed and simulated using a 1.5-μm-channel-length BiMOS process with 6000 equivalent gates. A discussion is presented of special features, function architecture, design strategies and tradeoffs involved at the various stages in the design of the VLSI (very-large-scale integration) chip. With a full complement of monitoring features and sophisticated performance parameters, the chip is very flexible and easy to use

Published in:

VLSI Technology, Systems and Applications, 1989. Proceedings of Technical Papers. 1989 International Symposium on

Date of Conference:

17-19 May 1989

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