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A half-micron manufacturable high performance CMOS technology applicable for multiple power supply applications

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7 Author(s)
Bhattacharyya, A. ; IBM Gen. Technol. Div., Essex Junction, VT, USA ; Mann, R. ; Nowak, E. ; Piro, R.
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A half-micron, manufacturable, high-performance CMOS technology that facilitates the transition from 5 V to 3.3 V product design by offering a common technology base with similar performance for applications at either power supply is described. Process integration and device design requirements that meet the following objectives are described: (1) a common process and device design base for VLSI (very-large-scale integration) circuit designs with 3.3 V and 5 V power supply applications without loss of performance at 3.3 V; (2) a performance improvement of 1.5× to 2× over preceding generations of CMOS (complementary metal-oxide-semiconductor) technology; (3) manufacturability; and (4) improved reliability of devices and gate dielectric. The common process base features improved process margin and key parameter control coupled with improved device design and selective scaling to yield 0.5-μm- and 0.7-μm-channel-length devices at 3.3 V and 5 V, respectively. Process variation from the common base is limited only to changes in oxide thickness and polysilicon gate width to meet dual power supply design compatibility. As examples a high-performance SRAM (static random-access memory) with sub-10-ns access and logic with sub-250-ps gate delay (<450 ps loaded) are presented

Published in:

VLSI Technology, Systems and Applications, 1989. Proceedings of Technical Papers. 1989 International Symposium on

Date of Conference:

17-19 May 1989