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An improved implantation scheme has been developed for a submicron retrograde twin-well CMOS (complementary metal-oxide-semiconductor) process. A blanket p-well implantation is used to avoid one photoresist step. The use of a phosphorus compensating implantation for PMOS (p-channel MOS) transistor threshold voltage control avoids another resist step and photoresist processing on gate oxide. The latter results in an improved gate oxide integrity. The new implantation scheme has been successfully employed in the fabrication of a 1-Mb SRAM (static random-access memory) on 150-mm wafers
Published in:
VLSI Technology, Systems and Applications, 1989. Proceedings of Technical Papers. 1989 International Symposium on
Date of Conference: 17-19 May 1989
- Page(s):
- 317 - 320
- Meeting Date :
- 17 May 1989-19 May 1989
- INSPEC Accession Number:
- 3677955
- Conference Location :
- Taipei
- Digital Object Identifier :
- 10.1109/VTSA.1989.68637
- Product Type:
- Conference Publications
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