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Power-supply considerations for future scaled CMOS systems

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1 Author(s)
Dennard, R.H. ; IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

The relationship between operating voltage, speed, and power consumption is examined for future proposed submicron (~0.5 μm) and deep submicron (0.25 μm) CMOS technologies for logic and static RAM applications. The scaling of DRAM (dynamic RAM) operating voltages to low levels is discussed. The practical problems associated with low-voltage power-supply regulation and distribution, either centrally in the system or on each chip, are considered. Interfacing chips with different voltage levels is also discussed

Published in:

VLSI Technology, Systems and Applications, 1989. Proceedings of Technical Papers. 1989 International Symposium on

Date of Conference:

17-19 May 1989