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LDS-ATPG: an automatic test pattern generation system for combinational VLSI circuits

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5 Author(s)
Sen-Chung Jiang ; Inst. of Electron., Nat. Chiao Tung Univ., Hsin-Chu, Taiwan ; Chung Len Lee ; Wen-Zen Shen, ; Jwu-E Chen
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An ATPG (automatic test pattern generation) system that consists of three optional test pattern generators and a fault simulator is presented. The three test pattern generators include a random pattern generator with the linear feedback shift register (LFSR) technique, a pseudorandom pattern generator, DISRUPT, and a deterministic test pattern generator, SLOPE1, which employs dynamic compaction to increase the fault coverage. The generators, together with a fault simulator, ACCEPT, generate test sets much smaller than those reported for other ATG systems while achieving the same or even better fault coverage with comparable system run times

Published in:

VLSI Technology, Systems and Applications, 1989. Proceedings of Technical Papers. 1989 International Symposium on

Date of Conference:

17-19 May 1989

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