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Spur reducing architecture of frequency synthesiser using switched capacitors

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3 Author(s)
Mandal, D. ; Electron. & Electr. Commun. Eng, Indian Inst. of Technol., Kharagpur, Kharagpur, India ; Mandal, P. ; Bhattacharyya, T.K.

This study presents a new spur reducing architecture of phase-locked loop-based frequency synthesiser. In the proposed architecture, an array of switched capacitors and a delay locked loop are used to evenly transfer the charge, coming from its charge pump, to its loop filter at a fixed number of equi-spaced time intervals. It reduces fundamental as well as higher-order harmonics of the reference spur. The proposed architecture has been designed and fabricated using 180 nm complementary metal oxide semiconductor technology. Measured result shows about 17.64 dB reduction of the fundamental spur compared with that of the conventional architecture.

Published in:

Circuits, Devices & Systems, IET  (Volume:8 ,  Issue: 4 )