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CMOS dynamic ternary circuit with full logic swing and zero-static power consumption

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2 Author(s)
Toto, F. ; Dipt. di Ingegneria dell''Inf. Elettronica Inf. Telecommun., Pisa Univ., Italy ; Saletti, R.

A new dynamic circuit scheme to realise ternary logic is presented. The main properties are the use of the standard CMOS process without any modification of the thresholds, the minimum possible number of external voltage levels (three), the highest possible logic swing and noise margins and the absence of static power consumption

Published in:

Electronics Letters  (Volume:34 ,  Issue: 11 )