By Topic

A Markov chain-based yield formula for VLSI fault-tolerant chips

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Ciciani, B. ; Dept. of Electron. Eng., Rome Univ., Italy ; Iazeolla, G.

A yield calculation method for the yield formula of fault-tolerant VLSI chips that improves existing methods and combines generalities, ease of computation, and predictability in approximation levels is presented. The method is concerned with the evaluation of the probability that a chip is acceptable given n defects. This is accomplished by introducing a Markov chain model in which each state represents an operating chip configuration, and the state transitions take place in the presence of manufacturing defects. Results from the comparison of this method to a method for memory chip yield evaluation, a method for the M-out-of-N yield problem evaluation, and a method for the square grid chip yield evaluation are presented

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:10 ,  Issue: 2 )