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A Markov chain-based yield formula for VLSI fault-tolerant chips

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2 Author(s)
B. Ciciani ; Dept. of Electron. Eng., Rome Univ., Italy ; G. Iazeolla

A yield calculation method for the yield formula of fault-tolerant VLSI chips that improves existing methods and combines generalities, ease of computation, and predictability in approximation levels is presented. The method is concerned with the evaluation of the probability that a chip is acceptable given n defects. This is accomplished by introducing a Markov chain model in which each state represents an operating chip configuration, and the state transitions take place in the presence of manufacturing defects. Results from the comparison of this method to a method for memory chip yield evaluation, a method for the M-out-of-N yield problem evaluation, and a method for the square grid chip yield evaluation are presented

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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:10 ,  Issue: 2 )