By Topic

Design of 622 Mbps ATM OAM functions for the integrated service access network

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Sangho Lee ; Broadband Commun. Dept., Electron. & Telecommun. Res. Inst., Seoul, South Korea

As the various types of application services are increased in the ATM (asynchronous transfer mode) network, it becomes a very important requirement for the ATM network equipment to provide for a higher transfer rate and to detect network failure or service degradation. In order to meet these requirements we develop a monolithic single chip device which can handle VPI/VCI address translation, cell appending, counting, and OAM (operation and management) processing for 65,536 VCs (virtual circuits) in real time. This paper describes the architectural design of a 622 Mbps ATM layer ASIC (application specific integrated circuit) which is under development. This ASIC is applicable for developing network equipment in B-ISDN. This supports both the NNI (network-network interface) and the UNI (user-network interface) and has ITU-TS based F4 or F5 level OAM function processing in real time. Also this chip can measure QoS (quality of service) and network parameters related to such OAM functions

Published in:

Communications, 1998. ICC 98. Conference Record. 1998 IEEE International Conference on  (Volume:3 )

Date of Conference:

7-11 Jun 1998