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A Highly Reliable 2-Bits/Cell Split-Gate Flash Memory Cell With a New Program-Disturbs Immune Array Configuration

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5 Author(s)
Liang Fang ; Shanghai Inst. of Microsyst. & Inf. Technol., Shanghai, China ; Jing Gu ; Bo Zhang ; Wei-Ran Kong
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A highly reliable 2-bits/cell split-gate flash memory cell in a novel program-disturbs immune array architecture is fabricated and demonstrated. Using a novel metal interconnect technique, a new virtual-ground array architecture is realized to greatly improve program disturbs as compared with conventional and-type configuration. A fully self-aligned process with shallow trench isolation in cell array is also proposed for the first time to fabricate this word-line shared split-gate structure without any lithomisalignment issue. Moreover, the negative charge trap in select gate (SG) oxide during conventional poly-to-poly Fowler-Nordheim tunneling erase operation is found as an important contribution to the cycling degradation for cells with thin SG oxide, and a negative control gate bias erase scheme is then presented to enhance the endurance reliability in this paper. A 250-°C baking experiment (before and after cycling) is performed to explore this cell's data retention characteristics, proving the free of extrinsic and intrinsic defect. Erase and program characteristics are comparable with conventional split-gate cell as well.

Published in:

Electron Devices, IEEE Transactions on  (Volume:61 ,  Issue: 7 )

Date of Publication:

July 2014

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