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Latency minimisation by system clock optimisation

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2 Author(s)
Sanghun Park ; Sch. of Electr. Eng., Seoul Nat. Univ., South Korea ; Kiyoung Choi

Performance of a system clock design depends on the operating clock period and cycle count, which is the same as the number of control steps for a design without loops. A method is proposed which maximises performance by adjusting the clock period and cycle count. Experimental results show that this method reduces the latency by 29.4% on average, compared to the conventional high-level synthesis method

Published in:

Electronics Letters  (Volume:34 ,  Issue: 9 )