By Topic

Latency minimisation by system clock optimisation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $33
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Sanghun Park ; Sch. of Electr. Eng., Seoul Nat. Univ., South Korea ; Kiyoung Choi

Performance of a system clock design depends on the operating clock period and cycle count, which is the same as the number of control steps for a design without loops. A method is proposed which maximises performance by adjusting the clock period and cycle count. Experimental results show that this method reduces the latency by 29.4% on average, compared to the conventional high-level synthesis method

Published in:

Electronics Letters  (Volume:34 ,  Issue: 9 )