Referenced Items are not available for this document.
Performance of a system clock design depends on the operating clock period and cycle count, which is the same as the number of control steps for a design without loops. A method is proposed which maximises performance by adjusting the clock period and cycle count. Experimental results show that this method reduces the latency by 29.4% on average, compared to the conventional high-level synthesis method
Published in:
Electronics Letters
(Volume:34
,
Issue:
9
)
Date of Publication: 30 Apr 1998
- Page(s):
- 862 - 864
- ISSN :
- 0013-5194
- INSPEC Accession Number:
- 5921623
- Digital Object Identifier :
- 10.1049/el:19980664
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- 30 Apr 1998
- Sponsored by :
- Institution of Engineering and Technology
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