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An experimental low-power CMOS pipeline ADC using feedforward sample-and-hold amplifier

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2 Author(s)
Chi-Tat Tam ; VLSI Res. Group, Waterloo Univ., Ont., Canada ; Elmasry, M.I.

This paper describes an experimental CMOS 3.3 V 10-bit 1.5-bit-per-stage pipeline analog-to-digital converter (ADC) using a feedforward sample-and-hold amplifier (SHA) in a 5 V 0.8 μm BiCMOS process. Test results show that it achieves up to 8 bits of resolution. The chip consumes a power of 35 mW at a maximum conversion rate of 10 MS/s. The modified SHA offers several advantages such as relaxed gain requirement, lower power consumption and smaller area

Published in:

Electrical and Computer Engineering, 1998. IEEE Canadian Conference on  (Volume:1 )

Date of Conference:

24-28 May 1998