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If the modulus of the digital delta-sigma modulator (DΔΣM) in a fractional- N frequency synthesizer is a power of two, then the output frequency is constrained to be a rational multiple of the phase detector frequency (fPD), where the denominator of the rational multiplier is a power of two. If the required output frequency is not related to fPD in this way, one is forced to approximate the ratio by using a small programmable modulus DΔΣM or a very large power-of-two modulus. Both of these solutions involve additional hardware. Furthermore, the programmable modulus solution can suffer from spurs, while the large power of two lacks accuracy. This paper presents a new solution, based on mixed-radix algebra, where the required ratio is formed by combining two different moduli. The programmable modulus solves the accuracy problem, while the large power-of-two modulus minimizes the spur content. In addition, the phase detector can be clocked at high speed. This paper explains the theoretical foundations of the method, elaborates a design methodology, and presents measured results for an 0.18 μm SiGe BiCMOS prototype.