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Delay analysis of series-connected MOSFET circuits

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2 Author(s)
Sakurai, T. ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; Newton, A.R.

In order to derive analytical delay expressions for CMOS gates in the submicrometer region, a realistic MOS model which incorporates an nth power law MOS model is developed. Closed-form delay formulas are obtained for CMOS inverters and series-connected MOSFET structures (SCMSs) that include short-channel effects. It is shown that the ratio of the delay of NAND/NOR to the delay of the inverter becomes smaller in the submicrometer region, because the VDS and VGS of each MOSFET in the SCMS are smaller than those of an inverter MOSFET. The smaller voltages in turn mitigate and relax the severe carrier velocity saturation in miniaturized MOSFETs. The results of the analysis for submicrometer VLSI designs show that if the maximum number of series-connected MOSFETs is considered to be five in 2-μm designs, then the number can be increased to six or seven in the submicrometer circuit design. In typical cases in VLSI designs, the delay ratio for N-SCMS is much less than N2. The delay dependence on input terminal position for SCMS structures is also described

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:26 ,  Issue: 2 )