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Defects in through-silicon vias (TSVs) due to fabrication steps decrease the yield and reliability of 3-D stacked integrated circuits, hence these defects need to be screened early in the manufacturing flow. Before wafer thinning, TSVs are buried in silicon and cannot be mechanically contacted, which severely limits the test access. Although TSVs become exposed after wafer thinning, probing on them is difficult because of TSV dimensions and the risk of probe-induced damage. To circumvent these problems, we propose a non-invasive method for pre-bond TSV test that does not require TSV probing. We use open TSVs as capacitive loads of their driving gates and measure the propagation delay by means of ring oscillators. Defects in TSVs cause variations in their resistor-capacitor parameters and therefore lead to variations in the propagation delay. By measuring these variations, we can detect the resistive open and leakage faults. We exploit different voltage levels to increase the sensitivity of the test and its robustness against random process variations. We provide a method to create a regression model to predict the defect size for a given measured period period of the ring oscillator, and a method for accuracy analysis. Results on fault detection effectiveness are presented through HSPICE simulations using realistic models for a 45 nm CMOS technology. The estimated design for testability area cost of our method is negligible for realistic dies.