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Topological constraints for E. F. Rent's work on microminiature packaging and circuitry

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4 Author(s)

Because of the wide impact of Mr. E. F. Rent's work in engineering, the applied sciences, and technology, the original memos of Mr. Rent and historically equivalent (HE) applications to today's complex integrated circuitry were published in the IBM Journal of Research and Development in 2005. It has been shown that evaluating existing wirelength distribution models with this HE interpretation of Rent's memos provides improved qualitative agreement with measurements and more accurate estimates of on-chip wirelength requirements for application-specific integrated circuit designs in the POWER4™ microprocessor core. Because of the increasing impact of Rent's work, including research on integration density for future computers and expansion to the fields of post-CMOS devices and bioengineering, this paper presents a review of these contributions and a new mathematical framework that explains the HE interpretation of Rent's memos. This framework provides topological constraints for today's ultralarge-scale integrated circuits, as well as a model that predicts this HE interpretation. The model arises from the underlying topology of the circuitry and interconnectivity of the circuit components. Using this model, predictions of the HE Rent parameters are obtained and show agreement to within - 5% to + 12% of the experimental values obtained from published data for the POWER4 microprocessor circuit designs.

Note: The Institute of Electrical and Electronics Engineers, Incorporated is distributing this Article with permission of the International Business Machines Corporation (IBM) who is the exclusive owner. The recipient of this Article may not assign, sublicense, lease, rent or otherwise transfer, reproduce, prepare derivative works, publicly display or perform, or distribute the Article.  

Published in:

IBM Journal of Research and Development  (Volume:58 ,  Issue: 2/3 )