By Topic

Test generation for (sequential) multi-valued logic networks based on genetic algorithm

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Keim, M. ; Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany ; Drechsler, N. ; Drechsler, R. ; Becker, B.

In this paper we present a test pattern generation tool for combinational Multi-Valued Logic Networks (MVLN) and Sequential Multi-Valued Logic Networks (SMVLN). The test pattern generator is based on a Genetic Algorithm. The tool can generator test patterns with respect to the stuck-at-fault model and skew fault model for SMVLNs with up to some thousand gates. A large set of experimental results is given to demonstrate the efficiency of the approach

Published in:

Multiple-Valued Logic, 1998. Proceedings. 1998 28th IEEE International Symposium on

Date of Conference:

27-29 May 1998