Test generation for (sequential) multi-valued logic networks based on genetic algorithm

In this paper we present a test pattern generation tool for combinational Multi-Valued Logic Networks (MVLN) and Sequential Multi-Valued Logic Networks (SMVLN). The test pattern generator is based on a Genetic Algorithm. The tool can generator test patterns with respect to the stuck-at-fault model and skew fault model for SMVLNs with up to some thousand gates. A large set of experimental results is given to demonstrate the efficiency of the approach.