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Neural network integrated circuits with single-block mixed-signal arrays

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4 Author(s)
Djahanshahi, H. ; Dept. of Electr. Eng., Windsor Univ., Ont., Canada ; Ahmadi, M. ; Jullien, G.A. ; Miller, W.C.

This paper discusses the design and implementation of a family of mixed-signal neural network integrated circuits for general and application-specific purposes. Regular arrays of a nonlinearly-loaded multiplier block form the core of multilayer neural networks. Input-output circuitry and network size, however, vary depending on design applications. Some features of the present architecture are highlighted through experimental study, namely, low characteristic variations and self-scaling property of neurons and reduced interconnection problems and areas on silicon. Other design issues such as supply voltage reduction and pin limitations are discussed together with fabrication test results.

Published in:

Signals, Systems & Computers, 1997. Conference Record of the Thirty-First Asilomar Conference on  (Volume:2 )

Date of Conference:

2-5 Nov. 1997