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Block cyclic redundancy check (CRC) codes are typically used to perform error detection in automatic repeat request (ARQ) protocols for data communications. Though efficient, CRCs can detect errors only after an entire block of data has been received and processed. In this work, we introduce a new "continuous" error detection scheme using arithmetic coding that provides a novel tradeoff between the amount of added redundancy and the amount of time needed to detect an error once it occurs. This method of error detection is achieved through the use of an arithmetic codec, and has the attractive feature that it can be combined physically with arithmetic source coding, which is widely used in state-of-the-art image coders. We analytically optimize the tradeoff between added redundancy and error-detection time, achieving significant gains in bit rate throughput over conventional ARQ schemes for binary symmetric channel models for all probabilities of error.
Signals, Systems & Computers, 1997. Conference Record of the Thirty-First Asilomar Conference on (Volume:2 )
Date of Conference: 2-5 Nov. 1997