By Topic

Using spatial information to analyze correlations between test structure data

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Kibarian, J.K. ; Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA ; Strojwas, A.J.

A modeling strategy that captures the dependence of performances on the spatial position of the chips on the wafer is presented. The information from this model can be used to determine whether the variance and correlation of parameters are due to random variation or are a function of wafer position. Simulation or knowledge from process engineers can be used to determine whether the spatial correlation between two parameters is due to a single underlying cause or multiple causes. The spatial correlation can also be used to split the correlation matrix into two parts: the first matrix would contain correlations due to spatially dependent disturbances and the second would contain those due to disturbances not spatially dependent.<>

Published in:

Microelectronic Test Structures, 1990. ICMTS 1990. Proceedings of the 1990 International Conference on

Date of Conference:

5-7 March 1990