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A wafer scale fail bit analysis system for VLSI memory yield improvement

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7 Author(s)
Y. Sakai ; Hitachi Ltd., Tokyo, Japan ; J. Sawada ; W. Sakamoto ; J. Murato
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A wafer-scale fail bit analysis system which outputs an entire wafer fail bit map (FBM) by using a data compaction technique and testing structure is developed. With this system, process defect locations on a wafer can easily be electrically recognized quickly. The processing time of wafer-scale fail bit analysis is reduced to only 2% of that required by the conventional method. An example of a wafer-scale FBM is shown.<>

Published in:

Microelectronic Test Structures, 1990. ICMTS 1990. Proceedings of the 1990 International Conference on

Date of Conference:

5-7 March 1990