By Topic

Yield modeling from SRAM failure analysis

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
H. G. Parks ; General Electric Co., Schenectady, NY, USA

Yield models based on Poisson, bose-Einstein, and binomial statistics are compared for a 1.25 mu m CMOS process. A mixed binomial yield model is shown to most accurately describe experimental yield data for a 1.25- mu m CMOS process. The model consists of gross yield and random yield components based on gross and random defects determined on a per level basis from a static random access memory-test element group (SRAM-TEG) yield vehicle failure analysis. The random yield component consists of both binomial and negative binomial segments, hence the mixed terminology, depending on whether or not a given defect shows evidence of clustering. Simple negative binomial models become optimistic at larger chip sizes by ascribing too much importance to interlevel effects of defect clustering. Using defect size distributions measured on a per level basis, the model is shown to hold over chip variations in feature size, product type, and chip area.<>

Published in:

Microelectronic Test Structures, 1990. ICMTS 1990. Proceedings of the 1990 International Conference on

Date of Conference:

5-7 March 1990