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Energy optimization of multilevel cache architectures for RISC and CISC processors

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3 Author(s)
Ko, U. ; Texas Instrum. Inc., Dallas, TX, USA ; Balsara, P.T. ; Nanda, A.K.

In this paper, we present the characterization and design of energy-efficient, on chip cache memories. The characterization of power dissipation in on-chip cache memories reveals that the memory peripheral interface circuits and bit array dissipate comparable power. To optimize performance and power in a processor's cache, a multidivided module (MDM) cache architecture is proposed to conserve energy in the bit array as well as the memory peripheral circuits. Compared to a conventional, nondivided, 16-kB cache, the latency and power of the MDM cache are reduced by a factor of 1.9 and 4.6, respectively. Based on the MDM cache architecture, the energy efficiency of the complete memory hierarchy is analyzed with respect to cache parameters in a multilevel processor cache design. This analysis was conducted by executing the SPECint92 benchmark programs with the miss ratios for reduced instruction set computer (RISC) and complex instruction set computer (CISC) machines.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:6 ,  Issue: 2 )

Date of Publication:

June 1998

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