By Topic

A VLSI inner product macrocell

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Breveglieri, L. ; Dipt. di Elettronica e Inf., Politecnico di Milano, Italy ; Dadda, L.

Microcontrollers for embedded computer applications require a library of dedicated macrocells for specific applications. Arithmetic and basic digital signal processor (DSP) computations may be too inefficient when computed by software on the core central processing unit (CPU) of the microcontroller. Here the architecture of a VLSI macrocell is defined and developed for the ST9 microcontroller (8 bits), for the computation of the inner (scalar) product of two vectors of integer numbers based on the multiply/accumulate algorithm. The arithmetic core of the macrocell is an integer pipeline. This macrocell fully interfaces to the ST9 environment and is optimized so as to achieve the maximum performances compatible with the bandwidth of the bus of ST9 and the minimum consumption of silicon area. The macrocell Is implemented in CMOSM5H technology (0.7 /spl mu/ channel width) and its performances, measured in terms of silicon area and throughput, are evaluated.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:6 ,  Issue: 2 )