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Fault-tolerant self-organizing map implemented by wafer-scale integration

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4 Author(s)
Yasunaga, M. ; Inst. of Inf. Sci. & Electron., Tsukuba Univ., Ibaraki, Japan ; Hachiya, I. ; Moki, K. ; Jung Hwan Kim

The self-organizing map (SOM) implemented by wafer-scale integration (WSI) will provide significantly high speed and desktop-size hardware for many practical applications such as pattern classification, image-processing, and robotics. Due to the synergistic effect of all neurons for ordering, the SOM-WSI is expected to reach the desired global-ordering state even in the presence of defective neurons. This fault tolerant capability, however, has not yet been studied. In this paper, we propose a fundamental SOM-WSI structure and its defect model. From the defect model, we derive a critical-stuck-output and show that if the defective neuron's stuck-output is larger than the critical-stuck-output, the defective SOM can eventually organize itself completely tolerating defects. In an ordinary digital design of a neuron, the critical-stuck-output is proved to be small. Therefore, we can expect high-fault tolerance in the SOM-WSI. Experiments are carried out by injecting defective neurons in a neurocomputer currently used as a prototype of the SOM-WSI. The experimental result agrees well with the proposed theory. In addition, we derive an equation to estimate the degree of fault-tolerance in the SOM hardware by expanding the critical-stuck-output calculation. The derived equation can be used to determine the fundamental design parameters in the SOM-WSI as well as other neurocomputer designs.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:6 ,  Issue: 2 )