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A novel approach for reducing the area occupied by contact pads on process control chips

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5 Author(s)
Walton, A.J. ; Dept. of Electr. Eng., Edinburgh Univ., UK ; Gammie, W. ; Morrow, D. ; Stevenson, J.T.M.
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An approach which reduces the number of pads required by electrical test structures is presented. The multiplexed scheme requires only two levels of interconnect and enables more devices to be located in a given area, providing the designer of test structures with more freedom to experiment with structures previously requiring a large number of pads. Applications for transistors, electrical verniers, yield monitoring, reliability evaluations, continuity tests, and measuring the resistance of tracks are discussed.<>

Published in:

Microelectronic Test Structures, 1990. ICMTS 1990. Proceedings of the 1990 International Conference on

Date of Conference:

5-7 March 1990