Referenced Items are not available for this document.
This paper describes a flexible MOS transistor layout generator which draws optimal layouts whatever the W and L dimensions. The drawing methodology is based on the use of small elementary parts, called bricks, which are placed side by side inside a user-specified boundary. The generated transistors may allow diffusion merging along whichever sides the user wishes and may have a global rectilinear shape. The internal structure of these cells may also be chosen by the designer so that it is well suited to his application. Transistors developed using this generator have been tested, and have been used to build a simple operational amplifier.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:33
,
Issue:
6
)
Date of Publication: June 1998
- Page(s):
- 896 - 903
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 5935165
- Digital Object Identifier :
- 10.1109/4.678653
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- June 1998
- Sponsored by :
- IEEE Solid-State Circuits Society
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