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FLAG: a flexible layout generator for analog MOS transistors

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5 Author(s)
H. Mathias ; Lab. d'Electron., Ecole Centrale de Lyon, Ecully, France ; J. Berger-Toussan ; G. Jacquemod ; F. Gaffiot
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This paper describes a flexible MOS transistor layout generator which draws optimal layouts whatever the W and L dimensions. The drawing methodology is based on the use of small elementary parts, called bricks, which are placed side by side inside a user-specified boundary. The generated transistors may allow diffusion merging along whichever sides the user wishes and may have a global rectilinear shape. The internal structure of these cells may also be chosen by the designer so that it is well suited to his application. Transistors developed using this generator have been tested, and have been used to build a simple operational amplifier.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:33 ,  Issue: 6 )