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Impact of epi facets on deep submicron elevated source/drain MOSFET characteristics

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2 Author(s)
J. J. Sun ; Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA ; C. M. Osburn

Deep submicron elevated source/drain (S/D) MOSFET's with epi facets, without facets, and with a second sidewall spacer covering the facets were studied using two-dimensional (2-D) process and device simulations. A slight degradation of drain-induced-barrier-lowering ΔVt (DIBL) has been projected due to the locally deeper junction beneath the epi facets. The locally deeper junction also shortens the S/D extension length if the spacer thickness is kept the same. The shorter extension in turn leads to a smaller parasitic resistance and therefore a higher device drive current. Gate-to-drain capacitance of the elevated S/D MOSFET is decreased as a result of faceting because of the reduced overlap area

Published in:

IEEE Transactions on Electron Devices  (Volume:45 ,  Issue: 6 )