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A low thermal budget self-aligned Ti silicide technology using germanium implantation for thin-film SOI MOSFET's

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3 Author(s)
Ping Liu ; Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA ; T. C. Hsiao ; J. C. S. Woo

In this paper, a titanium salicide technology with a very low thermal annealing temperature using germanium implantation for thin film SOI MOSFET's is investigated in detail. Ti silicide formation on the amorphous silicon generated by germanium implantation is studied. Compared to the conventional Ti salicide process, the Ti silicidation temperature is significantly lowered and the silicide depth is well controlled through the pre-amorphized layer. Therefore, the potential problems of the salicide process for SOI MOSFET's such as lateral voids, dopant segregation, thermal agglomeration, and increase of resistance on narrow gate are suppressed by germanium implantation. With the Ge pre-amorphization salicide process, a very low silicide contact resistance is obtained and sub-0.25-μm SOI MOSFET's are fabricated with good device characteristics

Published in:

IEEE Transactions on Electron Devices  (Volume:45 ,  Issue: 6 )