Self-aligned gate and source drain contacts in inverted-staggered a-Si:H thin-film transistors fabricated using selective area silicon PECVD

This article demonstrates full self-aligned inverted-staggered amorphous silicon thin-film transistors (TFT's) fabricated using selective plasma deposition of doped microcrystalline silicon source/drain contacts. Back-side exposure, using the bottom metal gate as the mask, produced the self-aligned contact openings. Selective deposition of the n+ silicon contact layer assures self-aligned ion resistance contacts and eliminates the need for reactive ion etching of the n+ silicon. Complete TFT fabrication requires no critical alignment steps. Transistors have linear mobility between 0.6 and 1.1 cm/sup 2//Vs, threshold voltage of 3.0 V, and sub-threshold slope of 0.35 V/decade. The OFF current is <10/sup -11/ A with -10 V gate voltage and 10 V between the source and drain, and ON/OFF ratios exceed 10.