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Design and Evaluation of Multiple Valued Logic Gates Using Pseudo N-Type Carbon Nanotube FETs

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4 Author(s)
Jinghang Liang ; Dept. of Electr. & Comput. Eng., Univ. of Alberta, Edmonton, AB, Canada ; Linbin Chen ; Jie Han ; Fabrizio Lombardi

Multiple valued logic (MVL) circuits are particularly attractive for nanoscale implementation as advantages in information density and operating speed can be harvested using emerging technologies. In this paper, a new family of MVL gates is proposed for implementation using carbon nanotube field-effect transistors (CNTFETs). The proposed designs use pseudo N-type CNTFETs and no resistor is utilized for their operation. This approach exploits threshold voltage control of the P-type and N-type transistors, while ensuring correct MVL operation for both ternary and quaternary logic gates. This paper provides a detailed assessment of several figures of merit, such as static power consumption, switching power consumption, propagation delay and the power-delay product (PDP). Compared with resistor-loaded designs, the proposed pseudo-NCNTFET MVL gates show advantages in circuit area, power consumption and energy efficiency, while still incurring a comparable propagation delay. Compared to a complementary logic family, the pseudo-NCNTFET MVL logic family requires a smaller circuit area with a similar propagation delay on average, albeit with a larger PDP and static power consumption. A design methodology and a discussion of issues related to leakage and yield are also provided for the proposed MVL logic family.

Published in:

IEEE Transactions on Nanotechnology  (Volume:13 ,  Issue: 4 )