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Software MPEG-2 video decoder on a 200-MHz, low-power multimedia microprocessor

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3 Author(s)
Nadehara, K. ; C&C Media Res. Lab., NEC Corp., Kawasaki, Japan ; Lieske, H. ; Kuroda, I.

This paper presents a low-power, 32-bit RISC microprocessor with a 64-bit “single-instruction multiple-data” multimedia coprocessor, V830R/AV, and its MPEG-2 video decoding performance. This coprocessor basically performs multimedia-oriented four 16-bit operations every clock, such as multiply-accumulate with symmetric rounding and saturation, and accelerates computationally intensive procedures of the video decoding; an 8×8 IDCT is performed in 201 clocks. The processor employs the Concurrent Rambus DRAM interface, and facilities for controlling cache behavior explicitly by software to speed up enormous memory accesses necessary for motion compensation. The 200-MHz V830R/AV processor with the 600-Mbyte/s Concurrent Rambus DRAMs decodes MPEG-2 MP@ML video in real-time (30 frames/s)

Published in:

Acoustics, Speech and Signal Processing, 1998. Proceedings of the 1998 IEEE International Conference on  (Volume:5 )

Date of Conference:

12-15 May 1998

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