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4-way superscalar DSP processor for audio codec applications

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7 Author(s)
Kim, Joon Seok ; Dept. of Electron. Eng., Yonsei Univ., Seoul, South Korea ; Sun Kook Yoo ; Sung Wook Park ; Nam Hoon Jung
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Audio codec (coding/decoding) algorithms are complex, of several coding techniques, and can be divided into DSP tasks, controller tasks and mixed tasks. The traditional DSP processor has been designed for fast processing of DSP tasks only, but not for controller and mixed tasks. This paper presents a new architecture that achieves high throughput on both controller and mixed tasks of such algorithms while maintaining high performance for DSP tasks. The proposed processor: YSP-3, operates four functional units (multiplier, two ALUs, load/store unit) in parallel via 4-issue super-scalar instruction structure. The performance evaluation of YSP-3 has been done through the implementation of the common DSP algorithms and the AC-3 decoder

Published in:

Acoustics, Speech and Signal Processing, 1998. Proceedings of the 1998 IEEE International Conference on  (Volume:5 )

Date of Conference:

12-15 May 1998

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