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A low-power VLSI feature extractor for speech recognition

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4 Author(s)
Felici, M. ; Dipt. di Elettronica Inf. e Sistemistica, Bologna Univ., Italy ; Borgatti, M. ; Ferrari, A. ; Guerrieri, R.

A low-power feature extraction chip computing cepstral coefficients from linear predictive analysis on one-bit quantized speech signals is presented and its VLSI implementation is evaluated. An isolated-word small-vocabulary speech recognizer based on these features has been developed. Its recognition accuracy is within 2% below a system based on standard linear predictive cepstral features. The power consumption of the feature extractor chip is 30 μW at 0.9 V

Published in:

Acoustics, Speech and Signal Processing, 1998. Proceedings of the 1998 IEEE International Conference on  (Volume:5 )

Date of Conference:

12-15 May 1998

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