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An efficient verifier for finite state machines

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2 Author(s)
Seung Ho Hwang ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; Newton, A.R.

The correctness-checking problem of a finite-state machine is considered. The concept of machine cover is revived and used as the basis of the formulation of the verification problem of the design correctness of finite-state machines. The concept of machine cover enables the verifier to efficiently check the sufficiency. The verifier checks to see if the implementation is correct with respect to its specification, which is given as a form of finite-state machine. Since in general the state encoding information is not available for verification purposes, it is assumed that the encoding information is missing. An efficient algorithm for the verification problem is presented along with its implementation. Experimental results show that the approach is promising in terms of speed

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:10 ,  Issue: 3 )